1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and in particular to a synchronous semiconductor memory device operating in synchronization with an external clock signal.
2. Description of the Background Art
With increase in operation speed of microprocessors (which will be referred to as "MPUs" hereinafter) in recent years, synchronous DRAMs (which will be referred to as SDRAMs hereinafter) and others operating in synchronization with clock signals have been used for achieving fast access of dynamic random access memories (which will be referred to as "DRAMs" hereinafter) and others used as main storage devices.
Internal operations of the SDRAM and others are controlled by dividing the operations into the row-related operation and the column related operation for control.
In the SDRAMs, structures in which a memory cell array is divided into banks each allowing independent operation have been employed for us allowing further fast operation. In each bank, the row-related operation and the column-related operation are controlled independently of each other.
As a result of increase in operation speed, the semiconductor memory devices such as SDRAMs suffer from the following problems during operation tests in manufacturing steps or outgoing tests.
With increase in storage capacity of the semiconductor memory device, a time required for the test increases, resulting in increase in cost for the test and increase in manufacturing cost of the product.
As countermeasures against increase in test time which is caused by the increased storage capacity of the semiconductor memory device, such a manner has first been employed that the test is carried out in parallel on a plurality of semiconductor memory devices for improving the test efficiency. However, the foregoing increased storage capacity of the semiconductor memory device increases the number of bits of an address signal applied to the semiconductor memory device, number of bits of a data I/O interface and others, and thus increases the numbers of input pins and I/O pins for the control signals in each semiconductor memory device. This restricts the number of semiconductor memory devices, which can be simultaneously tested in parallel.
The number of chips of the semiconductor memory devices, which can be simultaneously measured by one test operation of a tester device, depends on a relationship between the number of pins provided in a tester side and the number of pins required in the chip side, and can be generally expressed by the following formula: EQU (number of pins of tester)/(number of pins required in chip)&gt;(number of pins allowing simultaneous test)
Further, an extremely expensive tester device is required for increasing an operation speed of the tester device in accordance with an increased operation speed of the semiconductor memory device itself. This also increases the test cost.